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april 2004 copyright ? alliance semiconducto r. all rights reserved. ? as7c252mpfs18a 4/26/04, v.1.0 alliance semiconductor 1 of 22 2.5v 2m 18 pipelined burst synchronous sram features ? organization: 2,097,152 words 18 bits ? fast clock speeds to 200 mhz in lvttl/lvcmos ? fast clock to data access: 3.1/3.4/3.8 ns ?fast oe access time: 3.1/3.4/3.8 ns ? fully synchronous register-to-register operation ? single register flow-through mode ? single-cycle deselect - dual-cycle deselect also available (as7c252mpfd18a, as7c251mpfd32a/as7c251mpfd36a) ? asynchronous output enable control ? available in 100-pin tqfp and 165-ball bga packages ? individual byte write and global write ? multiple chip enables for easy expansion ? 2.5v core power supply ? linear or interleaved burst control ? snooze mode for reduced power-standby ? common data inputs and data outputs ? boundary scan using ieee 1149.1 jtag function ?ntd? 1 pipelined architecture available (as7c252mntd18a, as7c251mntd32a/ as7c251mntd36a) 1 ntd? is a trademark of allianc e semiconductor co rporation. all trademarks mentioned in this document are the property of their respective owners. logic block diagram selection guide -200 -167 -133 units minimum cycle time 5 6 7.5 ns maximum clock frequency 200 167 133 mhz maximum pipelined clock access time 3.1 3.4 3.8 ns maximum operating current 400 350 325 ma maximum standby current 120 110 100 ma maximum cmos standby current (dc) 70 70 70 ma burst logic adv adsc adsp clk lbo clk clr cs 21 19 21 a[20:0] 21 address d q cs clk register 2m x 18 memory array 18 18 dqb clk dq byte write registers dqa clk dq byte write registers enable clk dq register enable clk dq delay register ce output registers input registers power down dq[a,b] 2 ce0 ce1 ce2 bw b bw a oe zz oe ft clk clk bwe gwe 18
4/26/04, v.1.0 alliance semiconductor 2 of 22 as7c252mpfs18a ? pin and ball assignment 100-pin tqfp - top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 lbo a a a a a1 a0 nc a v ss v dd a a a a a a a a 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a ce0 ce1 nc nc bwb bwa ce2 v dd v ss clk gwe bwe oe adsc adsp adv a a tqfp 14 x 20mm a nc nc nc v ddq v ssq nc nc dqb0 dqb1 v ssq v ddq dqb2 dqb3 ft v dd nc v ss dqb4 dqb5 v ddq v ssq dqb6 dqb7 dqpb nc v ssq v ddq nc nc nc a nc nc v ddq v ssq nc dqpa dqa7 dqa6 v ssq v ddq dqa5 dqa4 v ss zz dqa3 dqa2 v ddq v ssq dqa1 dqa0 nc nc v ssq v ddq nc nc nc v dd nc
4/26/04, v.1.0 alliance semiconductor 3 of 22 as7c252mpfs18a ? ball assignment for 165-ball bga for 2m x 18 1 2 3 4 5 6 7 8 9 10 11 a nc a ce0 bwb nc ce2 bwe adsc adv aa b nc a ce1 nc bwa clk gwe oe adsp anc c nc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpa d nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa e nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa f nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa g nc dqb v ddq v dd v ss v ss v ss v dd v ddq nc dqa h ft v ss nc v dd v ss v ss v ss v dd nc nc zz j dqb nc v ddq v dd vss v ss v ss v dd v ddq dqa nc k dqb nc v ddq v dd vss v ss v ss v dd v ddq dqa nc l dqb nc v ddq v dd vss v ss v ss v dd v ddq dqa nc m dqb nc v ddq v dd vss v ss v ss v dd v ddq dqa nc n dqpb nc v ddq v ss nc a v ss v ss v ddq nc nc p nc nc a a tdi a1 1 1 a0 and a1 are the two least significant bits (lsb) of the addr ess field and set the internal burst counter if burst is desire d. tdo a a a a r lbo a a a tms a0 1 tck a a a a
? as7c252mpfs18a 4/26/04, v.1.0 alliance semiconductor 4 of 22 functional description the as7c252mpfs18a is a high-performance cmos 32-mbit synchronous static random access memory (sram) device organized as 2,097,152 words 18 bits. it incorporates a two- stage register-register pipeline for highest frequency on any giv en technology. fast cycle times of 5/6/7.5 ns with clock access times (t cd ) of 3.1/3.4/3.8 ns enable 200,167 and 133mhz bus frequencies. three chip enable (ce ) inputs permit easy memory expansion. burst operation is initiated in one of two ways: the controller address strobe (adsc ), or the processor address strobe (adsp ). the burst advance pin (adv ) allows subsequent internally generated burst addresses. read cycles are initiated with adsp (regardless of we and adsc ) using the new external address clocked into the on-chip address register when adsp is sampled low, the chip enables are sampled active, and the output buf fer is enabled with oe . in a read operation, the data accessed by the cu rrent address registered in the address registers by the positive edge of clk are carried to the data-out registers and driven on the output pins on the next positive edge of clk. adv is ignored on the clock edge that samples adsp asserted, but is sampled on all subsequent clock edges. address is incremented internally for the next access of the burst when adv is sampled low and both address strobes ar e high. burst mode is selectable with the lbo input. with lbo unconnected or driven high, burst operations use an interleaved count sequence. with lbo driven low, the device uses a linear count sequence. write cycles are performed by disabling the output buffers with oe and asserting a write comma nd. a global write enable gwe writes all 18 bits regardless of the state of individual bw[a,b] inputs. alternat ely, when gwe is high, one or more bytes may be written by asserting bwe and the appropriate individual byte bwn signals. bwn is ignored on the clock edge that samples adsp low, but it is sampled on all subsequent clock edges. output buffers are disabled when bwn is sampled low regardless of oe . data is clocked into the data input register when bwn is sampled low. address is incremented internally to the next burst address if bwn and adv are sampled low. this device operates in single- cycle deselect feature during read cycles. read or write cycles may also be initiated with adsc instead of adsp . the differences between cycles initiated with adsc and adsp follow. adsp must be sampled high when adsc is sampled low to initiate a cycle with adsc . we signals are sampled on the clock edge that samples adsc low (and adsp high). master chip enable ce0 blocks adsp , but not adsc . the as7c252mpfs18a family operates from a core 2.5v power supply. these devices are available in a 100-pin tqfp and 165-ball bga. tqfp and bga capacitance tqfp and bga thermal resistance parameter symbol test conditions min max unit input capacitance c in v in = 0v - 5 pf i/o capacitance c i/o v out = 0v - 7 pf description conditions symbol typical units thermal resistance (junction to ambient) 1 1 this parameter is sampled test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51 1?layer ja 40 c/w 4?layer ja 22 c/w thermal resistance (junction to top of case) 1 jc 8 c/w
4/26/04, v.1.0 alliance semiconductor 5 of 22 as7c252mpfs18a ? signal descriptions write enable truth table (per byte) key: x = don?t care, l = low, h = high, n = a, b; bwe , bwn = internal write signal. pin i/o properties description clk i clock clock. all inputs except oe , ft , zz, and lbo are synchronous to this clock. a,a0,a1 i sync address. sampled when all chip enables are active and when adsc or adsp are asserted. dq[a,b] i/o sync data. driven as output when the chip is enabled and when oe is active. ce0 isync master chip enable. sample d on clock edges when adsp or adsc is active. when ce0 is inactive, adsp is blocked. refer to the ?synchronous truth table? for more information. ce1, ce2 isync synchronous chip enables, active high, and active low, respective ly. sampled on clock edges when adsc is active or when ce0 and adsp are active. adsp i sync address strobe processor. asserted low to load a new address or to enter standby mode. adsc i sync address strobe controller. asserted low to load a new ad dress or to enter standby mode. adv i sync advance. asserted low to continue burst read/write. gwe isync global write enable. asserted low to write all 18 bits. when high, bwe and bw[a,b] control write enable. bwe i sync byte write enable. asserted low with gwe high to enable effect of bw[a:d] inputs. bw [a,b] i sync write enables. used to control wr ite of individual bytes when gwe is high and bwe is low. if any of bw[a,b] is active with gwe high and bwe low, the cycle is a write cycle. if all bw[a,b] are inactive, the cycle is a read cycle. oe i async asynchronous output enable. i/o pins are driven when oe is active and chip is in read mode. lbo istatic selects burst mode. when tied to v dd or left floating, device follow s interleaved burst order. when driven low, device follows linear burst order. this signal is inte rnally pulled high. tdo o sync serial data-out to the jtag circuit. deli vers data on the negative edge of tck (bga only). tdi i sync serial data-in to the jtag circuit. sampled on the rising edge of tck (bga only). tms i sync this pin controls the test access port state machine. sampled on the risi ng edge of tck (bga only). tck i test clock test clock. all inputs are sample d on the rising edge of tck. all outputs are driven from the falling edge of tck. ft istatic selects pipeline or flow-through mode. when tied to v dd or left floating, en ables pipeline mode. when driven low, enables single register flow-through mode. this signal is inte rnally pulled high. zz i async snooze. places device in low power mode ; data is retained. connect to gnd if unused. nc - - no connects function gwe bwe bwa bwb write all bytes lxxx hlll write byte a h l l h write byte b h l h l read hhxx hlhh
? as7c252mpfs18a 4/26/04, v.1.0 alliance semiconductor 6 of 22 burst sequence table synchronous truth table interleaved burst address linear burst address a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 a1 a0 starting address 0 0 0 1 1 0 1 1 starting address 0 0 0 1 1 0 1 1 first increment 0 1 0 0 1 1 1 0 first increment 0 1 1 0 1 1 0 0 second increment 1 0 1 1 0 0 0 1 second increment 1 0 1 1 0 0 0 1 third increment 1 1 1 0 0 1 0 0 third increment 1 1 1 0 0 1 1 0 ce0 1 1 x = don?t care, l = low, h = high ce1 ce2 adsp adsc adv write [2] 2 for write , l means any one or more byte write enable signals (bwa or bwb ) and bwe are low or gwe is low. write = high for all bwx , bwe , gwe high. see "write enable truth table (per byte)," on page 5 for more information. oe address accessed clk operation dq hxxxlx x x na l to h deselecthi ? z l l x l x x x x na l to h deselect hi ? z l l x h l x x x na l to h deselect hi ? z l x h l x x x x na l to h deselect hi ? z l x h h l x x x na l to h deselect hi ? z l h l l x x x l external l to h begin read q l h l l x x x h external l to h begin read hi ? z l h l h l x h l external l to h begin read q l h l h l x h h external l to h begin read hi ? z xxxhhl h l next l to hcontinue readq xxxhhl h h next l to hcontinue readhi ? z xxxhhh h l current l to hsuspend readq xxxhhh h h current l to hsuspend readhi ? z hxxxhl h l next l to hcontinue readq hxxxhl h h next l to hcontinue readhi ? z hxxxhh h l current l to hsuspend readq hxxxhh h h current l to hsuspend readhi ? z l h l h l x l x external l to h begin write d 3 3 for write operation following a read, oe must be high before the input data set up ti me and held high throughout the input hold time xxxhhl l x next l to hcontinue writed hxxxhl l x next l to hcontinue writed xxxhhh l x current l to hsuspend writed hxxxhh l x current l to hsuspend writed
4/26/04, v.1.0 alliance semiconductor 7 of 22 as7c252mpfs18a ? absolute maximum ratings stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions outsid e those indicated in the operational sections of this specificat ion is not implied. exposure to abso- lute maximum rating conditio ns may affect reliability. recommended operating conditions dc electrical characteristics * v il min = -1.5 for pulse wi dth less than 0.2 x t cyc i dd operating conditions and maximum limits parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.3 +3.6 v input voltage relative to gnd (input pins) v in ?0.3 v dd + 0.3 v input voltage relati ve to gnd (i/o pins) v in ?0.3 v ddq + 0.3 v power dissipation p d ?1.8w short circuit output current i out ? 20 ma storage temperature (tqfp) t stg (tqfp) ?65 +150 o c storage temperature (bga) t stg (bga) ?65 +125 o c temperature under bias t bias ?65 +135 o c parameter symbol min nominal max unit supply voltage for inputs v dd 2.375 2.5 2.625 v supply voltage for i/o v ddq 2.375 2.5 2.625 v ground supply vss 0 0 0 v parameter sym conditions min max unit input leakage current |i li |v dd = max, ov < v in < v dd -2 2 a output leakage current |i lo |oe v ih , v dd = max, ov < v out < v ddq -2 2 a input high (logic 1) voltage v ih address and control pins 1.7 v dd +0.3 v i/o pins 1.7 v ddq +0.3 v input low (logic 0) voltage v il address and control pins -0.3 * 0.7 v i/o pins -0.3 * 0.7 v output high voltage v oh i oh = ?4 ma, v ddq = 2.375v 1.7 ? v output low voltage v ol i ol = 8 ma, v ddq = 2.625v ? 0.7 v parameter sym conditions -200 -167 -133 unit operating power supply current 1 (pipelined mode) 1 i cc given with no output loading. i cc increases with faster cycle times and greater output loading. i cc ce0 = v il , ce1 = v ih , ce2 = v il , f = f max , i out = 0 ma 400 350 325 ma operating power supply current 1 (flow-through mode) i cc (ft) 325 280 260 ma standby power supply current i sb deselected, f = f max , zz < v il 120 110 100 ma i sb1 deselected, f = 0, zz < 0.2v, all v in 0.2v or v dd ? 0.2v 70 70 70 i sb2 deselected, f = f max , zz v dd ? 0.2v, all v in v il or v ih 60 60 60
? as7c252mpfs18a 4/26/04, v.1.0 alliance semiconductor 8 of 22 timing characteristics over operating range parameter sym ?200 ?167 -133 unit notes 1 1 see ?notes? on page 19. min max min max min max clock frequency f max ? 200 ? 167 ? 133 mhz cycle time (pipelined mode) t cyc 5?6 ?7.5? ns cycle time (flow -through mode) t cycf 7.5 ? 8.5 ? 12 ? ns clock access time (pipelined mode) t cd ? 3.1 ? 3.4 ? 3.8 ns clock access time (flow-through mode) t cdf ? 6.5 ? 7.5 ? 10 ns output enable low to data valid t oe ? 3.1 ? 3.4 ? 3.8 ns clock high to output low z t lzc 0 ? 0 ? 0 ? ns 2,3,4 data output invalid from clock high (pipelined mode) t oh 1.5 ? 1.5 ? 1.5 ? ns 2 data output invalid from clock high (flow-through mode) t ohf 3.0 ? 3.0 ? 3.0 ? ns 2 output enable low to output low z t lzoe 0 ? 0 ? 0 ? ns 2,3,4 output enable high to output high z t hzoe ? 3.0 ? 3.4 ? 3.8 ns 2,3,4 clock high to output high z t hzc ? 3.0 ? 3.4 ? 3.8 ns 2,3,4 output enable high to invalid output t ohoe 0?0 ? 0 ? ns clock high pulse width t ch 2.0 ? 2.4 ? 2.4 ? ns 5 clock low pulse width t cl 2.0 ? 2.3 ? 2.4 ? ns 5 address setup to clock high t as 1.4 ? 1.5 ? 1.5 ? ns 6 data setup to clock high t ds 1.4 ? 1.5 ? 1.5 ? ns 6 write setup to clock high t ws 1.4 ? 1.5 ? 1.5 ? ns 6,7 chip select setup to clock high t css 1.4 ? 1.5 ? 1.5 ? ns 6,8 address hold from clock high t ah 0.4 ? 0.5 ? 0.5 ? ns 6 data hold from clock high t dh 0.4 ? 0.5 ? 0.5 ? ns 6 write hold from clock high t wh 0.4 ? 0.5 ? 0.5 ? ns 6,7 chip select hold from clock high t csh 0.4 ? 0.5 ? 0.5 ? ns 6,8 adv setup to clock high t advs 1.4 ? 1.5 ? 1.5 ? ns 6 adsp setup to clock high t adsps 1.4 ? 1.5 ? 1.5 ? ns 6 adsc setup to clock high t adscs 1.4 ? 1.5 ? 1.5 ? ns 6 adv hold from clock high t advh 0.4 ? 0.5 ? 0.5 ? ns 6 adsp hold from clock high t adsph 0.4 ? 0.5 ? 0.5 ? ns 6 adsc hold from clock high t adsch 0.4 ? 0.5 ? 0.5 ? ns 6
4/26/04, v.1.0 alliance semiconductor 9 of 22 as7c252mpfs18a ? ieee 1149.1 serial boundary scan (jtag) the sram incorporates a serial boundary scan test access port (tap). the port operates in accordance with ieee standard 1149.1-1990. the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature if the jtag function is not being implemented, tck should be grounded to avoid mid-level input. at power-up, the device will come up in a reset state which will not interfere with the op eration of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tap controller receives commands from tms input. it is sampled on the rising e dge of tck. you can leave this pin/ball unconnected if the tap is not used. the pin/ball is pulled up internally, resulting in a logic high level. update-ir capture-ir shift-ir exit1-ir pause-ir exit2-ir select ir-scan update-dr capture-dr shift-dr exit1-dr pause-dr exit2-dr run-test/ idle test-logic reset select dr-scan 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 11 1 11 1 1 1 1 1 1 1 1 1 1 note: the 0 or 1 next to each state represents the value of tms at the rising edge of tck. tap controller state diagram tap controller block diagram selection circuitry selection circuitry 31 30 29 0 1 2 . . . boundary scan register 1 identification register bypass register instruction register x0 1 2 0 1 2 0 .. . .. tdi tms tck tdo tap controller 1 x = 75
? as7c252mpfs18a 4/26/04, v.1.0 alliance semiconductor 10 of 22 test data-in (tdi) the tdi pin/ball serially inputs information into the registers a nd can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register , see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an applicati on. tdi is connected to the most si gnificant bit (msb) of any register. test data-out (tdo) the tdo output pin/ball serially clocks data-out from the regi sters. the output is active depending upon the current state of the tap state machine. the output changes on the falling edge of tck. tdo is conn ected to the least significant bit (lsb) of any register. (see the tap controller state diagram.) performing a tap reset you can perform a reset by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram an d can be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi an d tdo pins/balls. they allow data to be scanned into and out of the sram test circuitry. only one register can be select ed at a time through the instru ction register. data is seri ally loaded into the tdi p in/ ball on the rising edge of tck. data is output on the tdo pin/ball on the falling edge of tck. instruction register you can serially load three-bit instructions into the instructio n register. the register is load ed when it is placed between th e tdi and tdo pins/balls as shown in the tap controller block diagram. the instruction regist er is loaded with the idcode instruction at power up and also if th e controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to all ow for fault isolation of the board- level series test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo pins/balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (vss) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bi directional pins/balls on the sram. the chip has a 76-bit-long register. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap cont roller is in the capture-dr state and is then placed between the tdi and td o pins/balls when the controller is move d to the shift-dr state. the extest, sample/preload, and sample z inst ructions can be used to captur e the contents of the i/o ring. the boundary scan order table shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the most significant bi t (msb) of the register is connected to tdi, and the least significant bit (lsb) is connected to tdo. identification (id) register the id register has a vendor code and other information described in the identification register definitions table. the id register is loaded with a vendor-specifi c, 32-bit code during the capture-dr stat e when the idcode co mmand is loaded in
4/26/04, v.1.0 alliance semiconductor 11 of 22 as7c252mpfs18a ? the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. tap instruction set eight different instructions are possible wi th the 3-bit instruction register. all comb inations are listed in the instruction c odes table. one of these instructions is reserved and should not be used. instructions are loaded into the tap cont roller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins/balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the inst ruction register is loaded with all 0s. extest is not implemented in this sram tap controller , and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 inst ruction. when an extest instruction is lo aded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions, unlike the sample/pr eload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the identification register. it also places the identification register betw een the tdi and tdo pins/balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins/balls when the tap controller is in a shift-dr state. it al so places all sram output s into a high-z state. sample/preload sample/preload is a standard 1149.1 mandatory public instru ction. when the sample/preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the ram?s input and i/o buffers into the boundary scan register. boundary scan register locations are not associated with an input or i/o pin, and are loaded with the default state id entified in the boundary scan chain table at the end of this section of the datasheet.because t he ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results ca nnot be accepted. ram input signals must be stabilized for long enough to meet the tap?s input data capture set-up plus hold time (tcs plus tch). the ram?s clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary scan register. moving the controller to shift-dr state then places the boundary scan register between the tdi and tdo pins. bypass the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. when the bypass instru ction is loaded in the instruction regist er and the tap is placed in a shift-dr state, the bypass register is placed between tdi and tdo. reserved do not use a reserved instruction. these instructions are not implemen ted but are reserved for future use.
? as7c252mpfs18a 4/26/04, v.1.0 alliance semiconductor 12 of 22 tap timing diagram tap ac electrical characteristics for notes 1 and 2, +10 o c t j +110 o c and +2.4v v dd +2.6v. description symbol min max units clock clock cycle time t thth 50 ns clock frequency f tf 20 mhz clock high time t thtl 20 ns clock low time t tlth 20 ns output times tck low to tdo unknown t tlox 0 ns tck low to tdo valid t tlov 10 ns tdi valid to tck high t dvth 5 ns tck high to tdi invalid t thdx 5 ns setup times tms setup t mvth 5 ns capture setup t cs 1 1 t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2 test conditions are specified using the load in the figure tap ac output load equivalent. 5ns hold times tms hold t thmx 5 ns capture hold t ch 1 5ns 123456 t thtl t tlth t thth t mvth t thmx t dvth t thdx t tlox t tlov test clock (tck) test mode select (tms) test data-in (tdi) te s t d a t a - o u t (tdo) don?t care undefined
4/26/04, v.1.0 alliance semiconductor 13 of 22 as7c252mpfs18a ? tap dc electrical characteristics and operating conditions (+10 o c < t j < +110 o c and +2.4v < v dd < +2.6v unless otherwise noted) 1. all voltage referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 1.5v for t t khkh/2 undershoot:v il (ac) -0.5 for t t khkh/2 power-up: v ih +2.6v and v dd 2.4v and v ddq 1.4v for t 200ms during normal operation, v ddq must not exceed v dd . control input signals (such as ld , r/w , etc.) may not have pulsed widths less than t khkl (min) or operate at frequencies exceeding f kf (max). description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current outputs disabled, 0v v in v ddq (dqx) il o -5.0 5.0 a output low voltage i olc = 100 av ol1 0.2 v 1 output low voltage i olt = 2ma v ol2 0.7 v 1 output high voltage i ohs = -100 av oh1 2.1 v 1 output high voltage i oht = -2ma v oh2 1.7 v 1 input pulse levels. . . . . . . . . . . . . . . vss to 2.5v input rise and fall times. . . . . . . . . . . . . . 1 ns input timing reference levels. . . . . . . . . . 1.25v output reference levels . . . . . . . . . . . . . .1.25v test load termination supply voltage. . . .1.25v tap ac test conditions tap ac output load equivalent tdo 50 ? z o =50 1.25v 20p
4/26/04, v.1.0 alliance semiconductor 14 of 22 as7c252mpfs18a ? identification register definitions scan register sizes instruction codes instruction field 2m x 18 description revision number (31:28) xxxx reserved for version number. device depth (27:23) xxxxx/xxxxx def ines the depth of 1m words. device width (22:18) xxxxx/xxxxx defines the width of x18 bits. device id (17:12) xxxxxx reserved for future use. jedec id code (11:1) 00000110100 allows un ique identification of sram vendor. id register presence indi cator (0) 1 indicates the presence of an id register. register name bit size instruction 3 bypass 1 id 32 boundary scan x18:76 instruction code description extest 000 captures i/o ring contents. plac es the boundary scan register be tween tdi and tdo. forces all sram outputs to high-z st ate. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not af fect sram operations. sample z 010 captures i/o ring contents. plac es the boundary scan register be tween tdi and tdo. forces all sram output drivers to a high-z state. reserved 101 do not use. this instru ction is reserved for future use. sample/ preload 100 captures i/o ring contents. places the bounda ry scan register between tdi and tdo. bypass 111, 011, 110 places the bypass register be tween tdi and tdo. this ope ration does not affect sram operations.
4/26/04, v.1.0 alliance semiconductor 15 of 22 as7c252mpfs18a ? 165-ball bga boundary scan exit order (x36) bit #s signal name ball id 39 clk 6b 40 ce2 6a 41 bwa 5b 42 nc 5a 43 bwb 4a 44 nc 4b 45 ce1 3b 46 ce0 3a 47 a 2a 48 a 2b 49 nc 1b 50 nc 1a 51 nc 1c 52 nc 1d 53 nc 1e 54 nc 1f 55 nc 1g 56 dqb 2d 57 dqb 2e 58 dqb 2f 59 dqb 2g 60 dqb 1j 61 dqb 1k 62 dqb 1l 63 dqb 1m 64 dqpb 1n 65 nc 2k 66 nc 2l 67 nc 2m 68 nc 2j 69 a 2r 70 lbo 1r 71 a 3p 72 a 3r 73 a 4r 74 a 4p 75 a1 6p 76 a0 6r bit #s signal name ball id 1a 6n 2a 8p 3a 8r 4a 9r 5a 9p 6 a 10p 7 a 10r 8a 11r 9a 11p 10 zz 11h 11 nc 11n 12 nc 11m 13 nc 11l 14 nc 11k 15 nc 11j 16 dqa 10m 17 dqa 10l 18 dqa 10k 19 dqa 10j 20 dqa 11g 21 dqa 11f 22 dqa 11e 23 dqa 11d 24 dqpa 11c 25 nc 10f 26 nc 10e 27 nc 10d 28 nc 10g 29 a 11a 30 nc 11b 31 a 10a 32 a 10b 33 adv 9a 34 adsp 9b 35 adsc 8a 36 oe 8b 37 bwe 7a 38 gwe 7b note 1 : nc and v ss pins included in the scan exit or der are read as ?x? (i.e. don?t care)
? as7c252mpfs18a 4/26/04, v.1.0 alliance semiconductor 16 of 22 key to switching waveforms timing waveform of read cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. bw[a,b] is don?t care. undefined or don?t care falling input rising input ce1 t cyc t ch t cl t adsps t adsph t as t ah t ws t advs t oh clk adsp adsc address gwe , bwe ce0 , ce2 adv oe d out t css t hzc t cd t wh t advh t hzoe t adscs t adsch load new address adv inserts wait states q(a2y10) q(a2y11) q(a3) q(a2) q(a2y01) q(a3y01) q(a3y10) q(a1) a2 a1 a3 (pipelined d out q(a2y10) q(a2y11) q(a3) q(a2y01) q(a3y01) q(a3y10) q(a3y11) q(a1) t hzc t oe t lzoe t csh (flow-through mode) mode) read q(a1) sus- pend read read q(a2) burst read q(a 2y01 ) read q(a3) dsel burst read q(a 2y10 ) suspend read q(a 2y10 ) burst read q(a 2y11 ) burst read q(a 3y01 ) burst read q(a 3y10 ) burst read q(a 3y11 )
4/26/04, v.1.0 alliance semiconductor 17 of 22 as7c252mpfs18a ? timing waveform of write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t cyc t cl t adsps t adsph t adscs t adsch t as t ah t ws t wh t css t advs t ds t dh clk adsp adsc address bwe ce0 , ce2 adv oe data in t csh t advh d(a2y01) d(a2y10) d(a3) d(a2) d(a2y01) d(a3y01) d(a3y10) d(a1) d(a2y11) adv suspends burst adsc loads new address a1 a2 a3 t ch ce1 bw[a:d] read q(a1) sus- pend write read q(a2) suspend write d(a 2 ) adv burst write d(a 2y01 ) suspend write d(a 2y01 ) adv burst write q(a 2y10 ) write d(a 3 ) burst write d(a 3y01 ) adv burst write q(a 2y11 ) adv burst write d(a 3y10 )
? as7c252mpfs18a 4/26/04, v.1.0 alliance semiconductor 18 of 22 timing waveform of read/write cycle note: y = xor when lbo = high/no connect; y = add when lbo = low. t ch t cyc t cl t adsps t adsph t as t ah t ws t wh t advs t ds t dh t oh clk adsp address gwe ce0 , ce2 adv oe d in d out t cd t advh t lzoe t oe t lzc q(a1) q(a3y01) d(a2) q(a3) q(a3y10) q(a3y11) a1 a2 a3 ce1 t hzoe (pipelined mode) d out q(a1) q(a3y01) q(a3y10) (flow-through mode) t cdf q(a3y11) dsel suspend read q(a1) read q(a1) suspend write d(a 2 ) adv burst read d(a 3y01 ) suspend read q(a 3y11 ) adv burst read q(a 3y10 ) adv burst read q(a 3y11 ) read q(a2) read q(a3)
4/26/04, v.1.0 alliance semiconductor 19 of 22 as7c252mpfs18a ? ac test conditions notes 1 for test conditions, see ?ac test conditions?, figures a, b, and c. 2 this parameter is measured with output load condition in figure c. 3 this parameter is sampled but not 100% tested. 4t hzoe is less than t lzoe , and t hzc is less than t lzc at any given temperature and voltage. 5t ch is measured as high if above vih, and t cl is measured as low if below vil. 6 this is a synchronous device. all addresses must meet the specified setup and hold tim es for all rising edges of clk. all othe r synchronous inputs must meet the setup and hold times for all rising edges of cl k when chip is enabled. 7 write refers to gwe , bwe , and bw[a,b] . 8 chip select refers to ce0 , ce1 , and ce2 . z 0 = 50 ? d out 50 ? figure b: output load (a) 30 pf* figure a: input waveform 10% 90% gnd 90% 10% +2.5v ? output load: for t lzc , t lzoe , t hzoe , t hzc , see figure c. for all others, see figure b. ? input pulse level: gnd to 2.5v. see figure a. ? input rise and fall time (measured at 0.25v a nd 2.25v): 2 ns. see figure a. ? input and output timing reference levels: 1.25v. v l = v ddq /2 thevenin equivalent: 353 ?/1538? 5 pf* 319 ?/1667? d out gnd figure c: output load(b) *including scope and jig capacitance +2.5v
4/26/04, v.1.0 alliance semiconductor 20 of 22 as7c252mpfs18a ? package dimensions 100-pin quad flat pack (tqfp) 165-ball bga (ball grid array) tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.85 16.15 he 21.80 22.20 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters a1 a2 l1 l c he e hd d b e / 0.500.05 ? ? 6 7 8 9 10 11 1 2 3 4 5 6 5 4 3 2 111 10 9 8 7 h d f e g a c b m p n r j l k 15.000.10 10.00 1.00 17.000.10 14.00 1.00 17.000.10 15.000.10 a1 corner index area all measurements are in mm. min typ max a 1.00 b 16.90 17.00 17.10 c 14.00 d 14.90 15.00 15.10 e 10.00 f 0.26 g 0.35 0.40 0.45 h 1.26 1.36 1.46 i 0.45 0.50 0.55 z z xy 0.400.05 1.46 max 0.26 0.70 0.20 z to p b o t t o m side view detail of solder ball a b c a e d d f h g h d f e g a c b m p n r j l k 0.12 z m m
4/26/04, v.1.0 alliance semiconductor 21 of 22 as7c252mpfs18a ? ordering information note: add suffix ?n? to the above part number s for lead free parts (ex as7c252mpfs18a-200tqc n) part numbering guide 1. alliance semiconductor sram prefix 2. operating voltage: 25 = 2.5v 3. organization: 2m = 2meg 4. pipelined/flow-through mode (each device works in both modes) 5. deselect: s = single cycle deselect 6. organization: 18 = x 18 7. production version: a = first production version 8. clock speed (mhz) 9. package type: tq = tqfp, b = bga 10. operating temperat ure: c = commercial ( 0 c to 70 c); i = industrial ( -40 c to 85 c) 11. n = lead free part package & width -200 -167 -133 tqfp x 18 as7c252mpfs18a-200tqc as7c252mpfs 18a-167tqc as7c252mpfs18a-133tqc as7c252mpfs18a-200tqi as7c252mpfs 18a-167tqi as7c252mpfs18a-133tqi bga x 18 as7c252mpfs18a-200bc AS7C252MPFS18A-167BC as7c252mpfs18a-133bc as7c252mpfs18a-200bi as7c252mpfs18a-167bi as7c252mpfs18a-133bi as7c 25 2m pf s 18 a ?xxx tq or b c/i x 1 23 45678 91011
alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel: 408 - 855 - 4900 fax: 408 - 855 - 4999 www.alsc.com copyright ? alliance semiconductor all rights reserved part number: as7c252mpfs18a document version: v.1.0 ? copyright 2003 alliance semiconductor corporation. all rights re served. our three-point logo, our name and intelliwatt are tr ademarks or registered trademarks of alli- ance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to mak e changes to this docu ment and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contai ned herein represents al liance's best data and/ or estimates at the time of issuance. allian ce reserves the right to change or correct this data at any time, without notice. i f the product described he rein is under develop- ment, significant changes to these specifications are possible. the information in this product data sheet is intended to be ge neral descriptive information for potential cus- tomers and users, and is not in tended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance d oes not assume any responsibility or liability arising out of the application or use of any product described herein, a nd disclaims any express or implied warranties related to the sale and/or use of alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellec tual property rights, except as express agreed to in alliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusivel y according to alliance's terms and condi- tions of sale. the purchase of products from alliance does not convey a license under a ny patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third part ies. alliance does not authorize its products for use as critical components in life-s upporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alli ance products in such life-sup porting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against all claims arising from such use. ? as7c252mpfs18a ?

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